Resistive non-volatile memory (NVM) may have a write pulse width distribution for different cells. Clock controlled ‘set’ and ‘reset’ may have the same pulse width for all NVM cells. The pulse width may be desired to meet the worst case (longest pulse width) with margin. The cells with short “set/reset” pulse width may be over written, which may increase the resistance distribution and reduce endurance of the cells. Thus, there may be a need for an advanced writing scheme.